FIG. 2 is a circuit diagram showing a core block of a conventional semiconductor memory device in which a DRAM (dynamic random access memory) is shown in particular as a typical example of MOS type semiconductor memory devices. In the DRAM shown in FIG. 2, the reading operation margin of each of memory cells is compensated for on the basis of each reference potential written in each reference cell. In more detail, in FIG. 2, a pair of bit lines B0 and B1 are connected to a bit line equalize circuit 31. The bit line equalize circuit 31 is connected to a sense amplifier circuit 32. A reference cell 23 is connected to the bit line B0 via a reference cell transfer gate 22. Further, the reference cell 23 is connected to a reference cell writing potential VREF via a reference potential writing gate 21. On the other hand, another memory cell 25 is connected to the bit line B0 via another memory cell transfer gate 24. Similarly, a reference cell 30 is connected to the bit line B1 via a reference cell transfer gate 28. Further, the reference cell 30 is connected to the reference cell writing potential VREF via a reference potential writing gate 29. On the other hand, another memory cell 27 is connected to the bit line B1 via another memory cell transfer gate 26.
A reference cell writing gate WG0 is connected to the reference potential writing gate 21. A reference cell select line RWL0 is connected to the reference cell transfer gate 22. A word line WL0 is connected to the memory cell transfer gate 24. On the other hand, a reference cell writing gate WG1 is connected to the reference potential writing gate 29. A reference cell select line RWL1 is connected to the reference cell transfer gate 28. A word line WL1 is connected to the memory cell transfer gate 26. Further, an equalize circuit activating signal EQL is given to the bit line equalize circuit 31. A sense amplifier activating signal SE is given to the sense amplifier circuit 32.